The expression “active layer” denotes a layer (or a plurality of sublayers) on which or in which components intended for applications, in particular, in the fields of microelectronics, optics and optoelectronics, will be manufactured.
A manufacturing process known from the prior art, illustrated in FIG. 1A, comprises the steps:                a) provision of a chamber 10 suitable for receiving the plurality of structures S,        b) circulation of a gas stream F (shown by the arrows) in the chamber 10 so that the chamber 10 has a non-oxidizing atmosphere,        c) heat treatment of the plurality of structures S at a temperature above a threshold value above which the oxygen present in the oxide of the dielectric diffuses through the active layer, reacts with the semiconductor material of the active layer, and produces a volatile material.        
The chamber provided during step a) is part of a device 1, and is equipped with a support system 4 suitable for supporting the structures S.
The non-oxidizing atmosphere may be obtained during step b) by a continuous gas stream F of an inert gas (such as argon) or a reducing gas. The term “non-oxidizing” is understood to mean an atmosphere that has an oxygen content of less than 10 ppm. The gas stream F is injected into the chamber 10 via an inlet 2 and is discharged from the chamber 10 via an outlet 3.
The heat treatment is carried out during step c) at a high temperature, conventionally of the order of 1200° C.
It should be noted that the steps b) and c) are preferably carried out simultaneously.
Such a prior art process is, in particular, used when the dielectric comprises silicon dioxide, and when the semiconductor material of the active layer comprises silicon. The volatile material produced then comprises silicon monoxide. Step c), therefore, makes it possible to partially dissolve the dielectric. Such a prior art process is particularly advantageous for the manufacture of structures requiring a dielectric thickness of less than 200 nm.
A person skilled in the art will find a technical description of such a process in the articles by Kononchuk (Kononchuk et al., “Novel trends in SOI technology for CMOS applications,” Solid State Phenomena, vols. 156-158 (2010), pp. 69-76, and also Kononchuk et al., “Internal Dissolution of Buried Oxide in SOI Wafers,” Solid State Phenomena, vols. 131-133 (2008), pp. 113-118).
However, such a prior art process is not completely satisfactory insofar as the applicants have observed that the dissolution of the dielectric during step c) is not uniform, which leads to a non-uniformity of the thickness of the dielectric in the structure manufactured. This non-uniformity is even more detrimental when the desired thickness of the dielectric is small (for example, less than 20 nm or 10 nm) and the diameter of the structure is large (300 mm or 450 mm).